This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the undesirable high negative temperature coefficient of low doped polysilicon layers that are often used as the load resistors in Static Random Access Memory, SRAM, cells.
As the demand to push semiconductor device features deeper into the sub-micron range has increased, numerous techniques have been developed for increasing the performance and circuit density of Static Random Access Memories (SRAMs), while also minimizing power dissipation. Most SRAM cells are implemented as cross-coupled inverters, which, in contrast to Dynamic Random Access Memories (DRAMs), do not require periodic refreshing in order to preserve the stored data as long as circuit power is maintained. Primarily, each of the cross-coupled inverters usually consist of an active transistor and a load resistor. For full CMOS SRAMs, the active transistor is usually an N channel device and the effective load resistor is usually a P channel device. For MOS SRAM, the active transistor is usually an N channel device and the load resistor is usually formed from high resistivity polysilicon. For typical SRAM cells, the above examples of cross-coupled inverters are used for information storage and two additional transistors are used for writing and reading information to and from the cells. Consequently, depending on the type of load resistor that is used, an SRAM cell can be comprised of 4 or 6 transistors. Choosing a particular SRAM technology for a given application involves numerous considerations. For minimal low standby power, full CMOS SRAM implementations are usually preferred. However, for simplicity, small cell size, low process cost and good speed performance, MOS implementations, such as NMOS, are often preferred.
MOS SRMAs, using polysilicon load resistors, can be implemented on large single P wells, while minimizing cell size and process complexity that would, otherwise, be needed to electrically isolate N and P channel devices. This has led to considerable popularity of four transistor, NMOS, SRAM (4T SRAM) technology. Although 4T SRAMs offer a number of attractive features, techniques for managing the evolving trade-offs between some cell failure concerns and excessive power dissipation have been a challenge. While lower SRAM operating currents are desirable for minimizing power dissipation, there are constraints an how low the operating currents can be. For example, SRAM cell failures can occur if excessive leakage currents become comparable to the on-state currents of the cell. In addition, the stored capacitive charge in the cell needs to be sufficient for protection from soft error failures, due to alpha particles. This, in turn, dictates that the operating currents of the cell be high enough to still allow for rapidly switching the memory state of the cell. Due, in part, to some of the above considerations between cell failures and excessive power dissipation. SRAMs have tended to use some evolving optimum value of cell operating current, while employing a number of techniques to maintain the operating current in a fairly constant optimal range. For 4T SRAMs, undesirable variations in optimal operating current are usually due to variations in the polysilicon load resistors, where the temperature coefficient of resistance, TCR, is often of great concern. Polysilicon resistors tend to exhibit rather large negative TCR values, which can lead to the problem of insufficient cell operating currents at low temperatures, for example.
Polysilicon resistors, as a controlling factor of SRAM operating currents, have been the subject of considerable attention.
U.S. Pat. No. 4,579,600 to Shah, et. al., teaches a method for using a two step process to reduce the large thermally activated grain boundary contribution to polysilicon sheet resistance that is typically responsible for a high negative TCR. A short high temperature annealing step is used to increase grain size and, thereby, reduce the number of grain boundaries as well as to reduce charge trapping at the grain boundaries. An additional step is taught for incorporating ionic hydrogen in the grain boundaries, as a means of achieving a further reduction of grain boundary trap density. By minimizing the grain boundary contribution to a negative TCR, the positive TCR contribution from the bulk of the grains is, therefore, able to be relatively more significant. Consequently, proper adjustment of the above extra process steps can be used to achieve a near zero TCR value. While addressing the problem of high negative TCR""s of polysilicon resistors, the time and expense for additional process steps may not always be compatible with manufacturing needs for an SRAM process.
U.S. Pat. No. 4,622,856 to Binder, et. al., teaches a method for obtaining precise polysilicon resistors, with low TCR values. High doping of the polysilicon is used to reduce the negative TCR contributed by the polysilicon grain boundaries, relative to the positive contribution to TCR from the bulk of the grains. Precision tailoring of the resultant polysilicon resistors is accomplished by laser trimming. However, the high level of polysilicon doping that is needed for reducing the negative TCR does not seem to be compatible with the need for very high valued polysilicon, SRAM, load resistors in the sub-gigaohm to high gigaohm range.
U.S. Pat. No. 4,579,600 to Bourassa, et. al., teaches a method for obtaining high valued polysilicon resistors, while minimizing an otherwise high negative TCR due to thermally activated grain boundaries. An additional masked ion implantation step is used to convert each polysilicon resistor line into two lateral disposed back-to-back PN junctions. The effective series resistance of the back-to-back diodes exhibits a much lower negative TCR than that of a uniformly doped polysilicon line with a comparable nominal resistor value. However, part of the cost for this benefit is an extra masking step and a minimum polysilicon resistor line length restriction for accommodating the photolithography ground rules associated with the additional masked, opposite conductivity, ion implant step.
U.S. Pat. No. 5,489,547 to Erdeljac, et. al., teaches a method for obtaining polysilicon resistors with moderate sheet resistance values and reduced values of negative TCR. An additional opposite conductivity ion implantation step is used to counter dope a previously ion implanted polysilicon resistor. The invention features the counter doping approach as a means of obtaining moderate polysilicon sheet resistance values without the need for additional process steps. However, such moderate values of sheet resistance do not seem to be compatible with the need for high polysilicon load resistors in the low-high gigaohm range, for 4T SRAMs.
There remains a need for a solution to the problem of reducing the negative TCR of polysilicon resistors and by means of a method that adds very little additional cost or time to a conventional 4T SRAM process, for example. The present invention solves this problem by forming a shallow vertical PN junction between the surface and sub-surface of the entire length of a polysilicon resistor. It is believed that the resultant space charge region (SCR) of the PN junction tends to adjust the effective electrical thickness of the polysilicon resistor, such as to make it thicker at colder temperatures. The effect of the changing SCR width with temperature helps to compensate the tendency for the thermally activated barrier of the grain boundaries to increase polysilicon sheet resistance at colder temperatures. This is accomplished by using an ion implantation process to form a shallow P type layer on the surface of a uniformly doped N type polysilicon resistor.
A principle object of the present invention is to provide an effective and manufacturable method to reduce the otherwise excessively high negative TCR of low doped polysilicon load resistors in sub-micron, 4T SRAM cells, over a semiconductor substrate.
Another object of the present invention is to minimize the negative TCR of polysilicon resistors by a novel PN junction approach which causes the electrical thickness of polysilicon resistors to effectively become thicker at colder temperatures, well below room temperature.
A further and primary object of the invention is to provide a method for forming vertical PN junctions along the entire length of polysilicon resistors, in order to obtain a temperature dependent space charge region for modulating their effective electrical thickness and, thereby, minimizing undesirably high negative TCR values.
These objects are achieved by a fabrication method which uses a shallow boron implantation process to form a PN junction, in the vertical direction, along the length of a polysilicon layer that has already been uniformly doped with a lower concentration of N type impurities. This new method comprises the steps of: (a) forming a photographically defined polysilicon resistor over a semiconductor substrate, which may include butted contacts to underlying source-drain regions and underlying conductive polysilicon lines, (b) lightly doping the polysilicon resistor with a low dose arsenic implant, (c) passivating the polysilicon resistor with a thin CVD oxide layer, (d) implanting a shallow high doped boron layer down through the CVD oxide layer and into the top surface of the polysilicon resistor, (e) high temperature annealing to activate the formation of a shallow PN junction over the surface of the polysilicon resistor and then (f) forming one or more electrical contact via holes down to the resultant, low TCR, polysilicon resistor, followed by conventional processing for the completion of a sub-micron 4T SRAM circuit.
This invention provides a method for solving the problem of being able to operate 4T SRAMs at cold temperatures, as low as xe2x88x9240xc2x0 C., while not appreciably adding to process complexity. This problem is mainly caused by the fact that polysilicon has two conduction components that exhibit opposing TCR behavior, namely: across grain boundaries and through grains. Conduction across grain boundaries is associated with a thermally activated barrier height, whereby the degree of conduction decreases with decreasing temperature. Conduction through the grains is controlled by the same temperature dependent free carrier, related, mobility physics as that for mono-crystalline silicon, whereby the degree of conduction increases with decreasing temperature. Accordingly, the grain boundary conduction exhibits a negative TCR and grain conduction exhibits a positive TCR. Unfortunately, in low doped polysilicon resistors, which is typical for conventional 4T SRAMs, the low doping causes the grain boundary barrier heights to be relatively high. Hence, the thermal behavior of grain boundary conduction tends to dominate over that of the grains. This high negative TCR problem is illustrated in FIG. 1, which shows a plot of polysilicon load resistance as a function of SRAM operating temperature, for the case of the prior art.
In order to compensate for the overriding high negative TCR of grain boundary conduction, the present invention creates a novel compensating effect by forming a shallow PN junction over the surface of the polysilicon resistor. It is believed that, for operation at cold temperatures, the temperature dependent width of the PN junction space charge region, SCR, appears to decrease. This, in turn, increases the effective electrical thickness of the polysilicon resistor. As shown in FIGS. 2a and 2b, this results in overall increased polysilicon conduction which helps to compensate for decreased grain boundary conduction. The above rationale for the behavior of polysilicon resistors, fabricated according to the present invention, does not seem to be consistent with what would be expected for single crystal silicon. However, the associated electrical results suggest that this, in effect, appears to be what is occurring. FIG. 2a shows plots of polysilicon load resistance vs SRAM operating temperature where the improvement, for two embodiments of the present invention, is compared to the behavior of the prior art. FIG. 2b is a normalized plot of the same data shown in FIG. 2a, where FIG. 2b shows that the present invention has reduced the TCR of the prior art by about a factor of two. As shown in FIGS. 2a and 2b, a substantial desired reduction in negative TCR is achieved with the present invention.